Timing Jitter in PLLs

1. What causes clock jitter?
2. What is jitter accumulation?
3. What is jitter transfer function?
4. What is ADC PLL?

What causes clock jitter?

Jitters in clock signals are typically caused by noise or other disturbances in the system. Contributing factors include thermal noise, power supply variations, loading conditions, device noise, and interference coupled from nearby circuits.

What is jitter accumulation?

Accumulated jitter, also known as long term jitter, is the deviation in the time of a given clock edge from when the same edge of an ideal clock occurs.

What is jitter transfer function?

The jitter transfer function gives the amount of jitter attenuation that will occur at a particular offset frequency. It is strongly affected by the loop bandwidth of the PLL, which is strongly affected by the PLL's low-pass loop filter. Accordingly, a PLL's response to jitter can be characterized as low-pass.

What is ADC PLL?

The first circuit, an analog-to-digital converter (“ADC”), uses feedback to generate the digital equivalent to an analog input voltage. The second circuit, a phase-locked loop (“PLL”), uses feedback to generate a signal matched in frequency to the input signal—or to some multiple of that frequency.