Howtosignalprocessing
- What is cycle slipping?
- What will happen if you set the PLL incorrectly?
- What does PLL bandwidth mean?
- How is PLL frequency calculated?
What is cycle slipping?
A cycle slip is a discontinuity in a receiver's phase lock on a satellite's signal. A power loss, a very low signal-to-noise ratio, a failure of the receiver software, a malfunctioning satellite oscillator can cause a cycle slip. It can also be caused by severe ionospheric conditions.
What will happen if you set the PLL incorrectly?
Incorrect information sent to the PLL can easily cause it not to lock. Some of the more common programming errors include a VCO programmed to a frequency out of range, incorrect settings for VCO calibration or incorrect timing of the registers.
What does PLL bandwidth mean?
PLL bandwidth is the measure of the PLL's ability to track the reference clock and its associated jitter. Bandwidth is approximately the unity gain point for open loop PLL response.
How is PLL frequency calculated?
N = [A × (P + 1)] + [(B – A) × P] = AP + A + BP – AP = BP + A. Therefore, FOUT = (FREF/R) × (BP + A), as in Figure 4. There are many specifications to consider when designing a PLL. The input RF frequency range and the channel spacing determine the value of the R and N counter and the prescaler parameters.
