Howtosignalprocessing
- What is the sampling rate of an ADC?
- How do you reduce ADC sampling rate?
- How does ADC increase sampling rate?
What is the sampling rate of an ADC?
The sampling rate is the frequency expressed in Hertz (Hz) at which the ADC samples the input analogue signal. As mentioned before, the sampling interval is the time between successive samples: the sampling rate is thus the inverse of the sampling interval.
How do you reduce ADC sampling rate?
Increasing sampling time will slow down the rate. Slowing down the ADC clock will also slow down the sampling rate. Otherwise, you should set it up to trigger off of a timer, and set the timer to the desired sampling frequency. That's the common approach.
How does ADC increase sampling rate?
To increase the sampling rate of an ADC whose comparators are already running at maximum speed, the number of upper (coarse) and lower (fine) quantizer blocks must be extended. This can be achieved by implementing an N-bit, coarse ADC and two time-interleaved, N-bit, fine ADCs (Figure 2).
